UMC, Cadence Collaborate on Analog/Mixed-Signal Flow for 22ULP/ULL Process Technologies
August 24, 2022 | Business WireEstimated reading time: 2 minutes
United Microelectronics Corporation (UMC), a leading global semiconductor foundry, and Cadence Design Systems, Inc. announced that the Cadence® analog/mixed-signal (AMS) IC design flow has been certified for UMC’s 22ULP/ULL process technologies. This flow optimizes process efficiency and shortens design cycle time, accelerating the development of 5G, IoT and display application designs to meet increasing market demand.
UMC’s 22nm process features ultra-low power consumption and ultra-low leakage to meet various application requirements including extended battery life, a small form factor, and strong computing capabilities. The UMC-certified Cadence AMS flow provides a Unified Reliability Interface (URI), which enables customers to better monitor the circuit’s reliability and service life when designing on UMC’s 22ULP/ULL processes while achieving an ideal balance between cost and performance. The Cadence AMS flow also includes an actual demonstration circuit, which users can apply during design to enhance efficiency and precision.
The Cadence AMS flow consists of integrated solutions and methodologies enabled by the UMC 22nm process design kit (PDK) to speed a design to completion:
- The Virtuoso® design platform, including schematic editing, the analog design environment (ADE), and layout XL tool enablement.
- Spectre® AMS Designer, which combines the power of the Spectre X Simulator and the Xcelium™Logic Simulation engine to provide consistent and accurate results of designs consisting of transistor, behavioral, timing and parasitic block representations.
- Voltus™-Fi Custom Power Integrity Solution provides electromigration and IR drop (EM-IR) analysis, which lets users quickly input the required EM rules.
“UMC is committed to providing leading foundry solutions and advanced specialty technologies that meet the requirements of applications in fast-growing markets such as 5G, IoT, and display,” said Osbert Cheng, vice president of device technology development & design support at UMC. “When compared with 28nm capabilities, UMC's 22ULP/ULL process technologies can reduce chip die area by 10%, provide better power efficiency, and enhance radio frequency performance. Through this collaboration with Cadence, we are providing customers with an industry-leading design solution, enabling greater efficiency and speeding time to market.”
"With the increasing design complexity of 5G, IoT and smart wearables, enhancements in analog and mixed-signal technology are critical for the success of advanced IC designs,” said Ashutosh Mauskar, vice president, product management in the Custom IC & PCB Group at Cadence. “The Cadence AMS flow that has been optimized for use on UMC’s 22ULP/ULL process technologies, provides customers with comprehensive solutions across design, verification and implementation. By collaborating with UMC, we’re enabling mutual customers to rapidly achieve innovative mixed-signal designs on 22ULP/ULL.”
Download The System Designer’s Guide to… System Analysisby Brad Griffin along with its companion book The Cadence System Design Solutions Guide.You can also view other titles in our full I-007eBooks library.
Suggested Items
Real Time with… IPC APEX EXPO 2024: My Role as a Technology Solutions Director
05/02/2024 | Real Time with...IPC APEX EXPOPeter Tranitz, senior director of technology solutions at IPC, shares insights into his role as the design initiative lead. He details his advocacy work, industry support, and the responsibilities of the design initiative committee. The conversation also covers the revamping of standards, the IPC Design Competition, and the implementation of design rules in software tools.
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.
IPC's Vision for Empowering PCB Design Engineers
04/30/2024 | Robert Erickson, IPCAs architects of innovation, printed circuit board designers are tasked with translating increasingly complex concepts into tangible designs that power our modern world. IPC provides the necessary community, standards framework, and education to prepare these pioneers as they explore the boundaries of what’s possible, equipping engineers with the knowledge, skills, and resources required to thrive in an increasingly dynamic field.
On the Line With… Talks With Cadence Expert on SI/PI for PCB Designers
05/02/2024 | I-Connect007In “PCB 3.0: A New Design Methodology—SI/PI for PCB Designers,” subject matter expert Brad Griffin, Cadence Design Systems, discusses how an intelligent system design methodology can move some signal and power integrity decision-making into the physical design space, offering real-time feedback.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.