Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack
November 18, 2021 | Cadence Design Systems, Inc.Estimated reading time: 2 minutes
Cadence Design Systems, Inc., a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE™), announced that Samsung Foundry has qualified the Cadence® Integrity™ 3D-IC platform’s 2D-to-3D native 3D partitioning flow. Using the new flow, customers can partition existing 2D designs into 3D memory-on-logic configurations and achieve better power, performance and area (PPA) with a homogeneous 3D stack when compared with the original 2D design. The flow also provides robust 3D-IC system planning, implementation and early analysis capabilities for the partitioned design, which is ideal for customers creating complex, next-generation hyperscale computing, mobile, automotive and AI applications.
Hitting a memory wall where RAM access cannot keep pace with CPU execution speed causes the overall system to slow down due to memory latency. One way to overcome this is to place memories on top of the logic in a homogenous stacking configuration. The configuration, when mounted on the same package, reduces wirelength and area and speeds up memory access, thus helping to improve the performance of the CPU core.
The Integrity 3D-IC platform’s 3D partitioning enables the user to separate out memory macros and standard cells and place them on two different dies within a 3D homogeneous stack. The automated flow performs partitioning and full implementation of the 3D stack while building connections between the macros and standard cells. Once the contents of each die are finalized, the system and package can be implemented in the Integrity 3D-IC platform, enabling bump planning, implementation, co-design with other dies, and early analysis of thermal, power and static timing analysis (STA).
“Customers faced with varying automated partitioning requirements for 3D-IC configurations can take advantage of this unique capability in Samsung Foundry’s MDI reference flow based on Native 3D partitioning in Cadence’s new Integrity 3D-IC platform to explore the effects of chip stacking,” said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. “This successful cooperation between Cadence and Samsung provides customers with a partitioning, implementation and analysis flow for stacked 3D designs that enables them to reduce power consumption and area while improving overall system performance.”
“Through our ongoing collaboration with Samsung Foundry, we’ve collaborated to innovate in the area of multi-die implementation and deliver automated Native 3D partitioning flows,” said Vivek Mishra, corporate vice president, Product Engineering in the Digital & Signoff Group at Cadence. “Samsung Foundry’s advanced packaging for multi-die implementation, combined with Cadence’s unified Integrity 3D-IC platform, provides our mutual customers with robust multi-die solutions.”
The Integrity 3D-IC platform provides customers with a common cockpit and database, a complete planning system, seamless implementation tool integration, integrated system-level analysis capabilities and an easy-to-use interface and lets users co-design with the Virtuoso® Design Environment and Allegro® packaging technologies. The platform also includes a broader Cadence 3D-IC solution portfolio including the Voltus™ IC Power Integrity Solution for power delivery network (PDN) analysis, Celsius™ Thermal Solver for 3D thermal analysis, Tempus™ Timing Signoff Solution for 3D signoff timing and Pegasus™ Verification System for system layout-versus-schematic (LVS).
Suggested Items
Altus Group Helps BitBox Unlock Productivity and Efficiency Gains with New Reflow Oven
04/22/2024 | Altus GroupAltus Group, a leading provider of capital equipment, has recently assisted BitBox, a UK-based electronics design, engineering and manufacturing company in upgrading its operations with the implementation of a new reflow oven from Heller Industries.
Real Time with... IPC APEX EXPO 2024: Exploring IPC's PCB Design Courses with Kris Moyer
04/18/2024 | Real Time with...IPC APEX EXPOGuest Editor Kelly Dack and IPC instructor Kris Moyer discuss IPC's PCB design training and education offerings. They delve into course topics such as design fundamentals, mil/aero, rigid-flex, RF design, and advanced design concepts. They also highlight material selection for high-speed design, thermal management, and dissipation techniques. The interview wraps up with details about how to access these courses online.
Cadence Unveils Palladium Z3 and Protium X3 Systems
04/18/2024 | Cadence Design SystemsThe Palladium Z3 and Protium X3 systems offer increased capacity, and scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models, ensuring proper functionality and performance.
Signal Integrity Expert Donald Telian to Teach 'Signal Integrity, In Practice' Masterclass Globally
04/17/2024 | PRLOGDonald Telian and The EEcosystem announce the global tour of "Signal Integrity, In Practice," a groundbreaking LIVE masterclass designed to equip hardware engineers with essential skills for solving Signal Integrity (SI) challenges in today's fast-paced technological landscape.
On the Line With... Podcast Talks With Cadence Expert on Manufacturing
04/18/2024 | I-Connect007In “PCB 3.0: A New Design Methodology: Manufacturing” Patrick Davis returns to the podcast to talk about design rules. As design considerations become more and more complex, so, too, do the rulesets designers must abide by.